1. Field of the Invention
The present invention relates to the field of memory technologies, and particularly to a common centroid differential sensing scheme.
2. Description of the Related Art
Numerous integrated circuit systems utilize differential sensing schemes to sense the contents of their registers. A differential sensing scheme rapidly detects the content of a memory cell by sensing a differential signal between two complementary differential output bit lines (that couple to the memory cell) and decoding this differential signal to predict the content of the memory cell.
FIG. 1 sets forth one example of a differential sensing scheme used to read the contents of a MOS RAM array. As shown in this figure, each register in this memory cell array provides its output on two complementary bit lines Y.sub.NA and Y.sub.NB (where N represents an integer) that traverse the length of the column in which the register is located. For example, if decoders 100 and 105 identify register 1-1 as the appropriate register to output its content, register 1-1 (1) leaves the signal on Y.sub.1A line high and pulls the signal on Y.sub.1B line low if this register has a "one" stored, or (2) pulls the signal on Y.sub.1A line low and leaves the signal on Y.sub.1B line high if it has a "zero" stored. As further shown in FIG. 1, sense amplifier 110 then quickly identifies the content of register 1-1 by detecting a differential signal between the two complementary output bit lines Y.sub.1A and Y.sub.1B.
Currently, a number of differential sensing schemes have high precision sense amplifiers that sense differential signals at very small differential values, such as 100-200 mVs. Unfortunately, prior art differential sensing schemes cannot fully take advantage of these high precision sense amplifiers because unpredictable capacitive effects on the differential output bit line pairs reduce the differential sensing speed by increasing the time necessary to generate a detectable differential signal (e.g., the time necessary to generate a 200 mV differential signal).
A capacitive offset induced degradation of a sensed differential input signal to a sense amp lengthens the read access time of the memory or register (i.e., producing a "push-out" in the read occur time). This problematic effect, is compounded in that the access time push-out is random and data pattern sensitive. Having this access time being variable means that the access speed is limited by the capacitive condition that causes the worst access time.
Furthermore, most high-speed memories and registers employ sense-amps that are critically enabled in time. This enabling of the sense-amp must occur only after the proper differential signal has been developed on the bit line pair and not before. This sense-amp enabling signal is typically self-timed, that is, it is generated by asynchronous timing circuitry to closely match the time that is required to build up the differential bit line signal. As we can see, having a differential signal generation that can have a random and a data pattern dependency in its signal build up time due to capacitive offsets is highly undesirable. These effects will cause the sense-amp enabling signal to be necessarily delayed in order to ensure the proper differential signal build up in the worst case condition.
Thus, it is desirable to provide a way is to negate the effects of unbalanced capacitive coupling to the bit lines in order to realize predictable access times across the array and hence, tune the sense-amp enabling signal to realize the fastest possible access time with confidence in the differential bit line signals across the arrays.
These unpredictable capacitive effects on the output bit line pairs include (1) capacitive coupling between adjacent unrelated bit lines, and (2) capacitance offset of related output bit lines due to the two-dimensional parasitic capacitance gradients across the output bit lines. For example, as shown in FIG. 2, if output bit line Y.sub.A(N-1) of column N-1 is high and output bit line Y.sub.B(N+1) of column N+1 switches low during a read sense operation, (where the sensing condition is Y.sub.BN going low, and Y.sub.AN staying high), the time necessary to develop a positive differential signal between the output bit lines of column N is increased, because bit line Y.sub.A(N-1) attempts to maintain the signal on bit line Y.sub.BN high, while bit line Y.sub.B(N+1) attempts capacitively couple the signal on bit line Y.sub.AN low. In other words, under certain circumstances, the capacitive coupling due to unrelated neighbor bit lines can oppose the generation of a differential signal between a differential output bit line pair. The net result is a "push out" of the memory access time.
In addition, the speed of generation of a differential signal between a differential output bit line pair is also adversely affected by the two-dimensional parasitic capacitance gradient formed across the differential output bit lines. The capacitance gradient affects the differential signal generation speed because it introduces a capacitance voltage offset between the bit lines of a differential pair (i.e., causes the capacitance of the bit lines of a differential pair to differ). A parasitic capacitance gradient across a differential pair can be due to the particular memory cell's layout, to the process used to construct the registers, to the topography of the underlying circuitry, and to the misalignment of the photo-masks used in processing.
FIG. 3 presents a diagram of the differential output bit line pairs of a prior art differential sensing scheme. As shown in this figure, prior art differential sensing scheme 300 utilizes a simple swapping technique, which equalizes the capacitive coupling effect due to adjacent unrelated bit lines by causing the output bit lines in a particular column to feel the capacitive effect of all four adjacent unrelated bit lines in an equal manner. Thereby eliminating the data dependency, making all sensing transactions see a uniform capacitive coupling from "neighbors."
More specifically, the capacitive effects of the adjacent unrelated bit lines Y.sub.A(N-1) and Y.sub.B(N+1) on bit lines Y.sub.BN and Y.sub.AN equally effect the differential signal generation speed between these column N output bit lines, because these capacitive effects are equalized by the capacitive effects of the adjacent unrelated bit lines Y.sub.B(N-1) and Y.sub.A(N+1) on bit lines Y.sub.BN and Y.sub.AN. For example, as shown in FIG. 4, the speed necessary to develop a positive differential signal between bit lines Y.sub.BN and Y.sub.AN is not reduced even when output bit line Y.sub.A(N-1) is high and output bit line Y.sub.B(N+1) is low, because the capacitive effects due to these bit lines is opposed by and equalized by the capacitive effects due to bit lines Y.sub.B(N-1) and Y.sub.A(N+1).
As seen in FIG. 3, this conventional method of physically swapping or switching the bit line pairs along the columns of the array does, to the first order, solve the mentioned problems with both data dependent (coupling from neighboring bit lines) and random (parasitic capacitive offsets up and down a column) capacitive offsets.
However, for differential output bit line pairs that swap only once (e.g., the differential output bit line pairs of columns N-2, N, N+2 in FIG. 3), this prior art technique does not eliminate the capacitive offset effect due to a two-dimensional parasitic capacitance gradients directed across the differential output bit line pairs. This sort of effect may be introduced during the processing of the integrated circuit due to a skew in the photomask alignment along the column of a very large array. In other words, even after this simple swapping technique, there can be a capacitance offset between the bit lines of differential pairs that only swap once. The capacitance offset can in turn decrease the differential sensing speed of differential sensing apparatus 300 by increasing the time necessary to generate a detectable differential signal. Consequently, it is desirable to provide a differential sensing scheme which not only eliminates the capacitive coupling between adjacent unrelated bit lines, but also eliminates the capacitive offset between related differential bit lines due to two-dimensional parasitic capacitance gradients directed across these bit lines.